1. Field of the Invention
The present invention relates to a timing signal generator circuit for use in a signal waveform measurement system for measuring multi-channel on-chip signal waveforms on fixed voltage interconnection lines of, for example, an internal signal, a power voltage, a ground voltage, a well voltage, a substrate voltage and so on of a semiconductor very large scale integrated circuit (hereinafter referred to as a VLSI).
2. Description of the Related Art
Circuits to be mounted on chips are increased in scale in accordance with scale shrinkage of semiconductor manufacturing processes, and lately a mixed signal system LSI in which different kinds of signal processing functions, such as analog and digital or high-frequency wireless communication processing and baseband data processing, are integrated together on a single chip is general. However, in such an LSI having a configuration in which a number of function circuits are interconnected inside a chip, the operating states of the function circuits cannot therefore be observed from outside the chip, and this has made it difficult to analyze failures at the time of malfunctioning. On the other hand, it becomes more important to consider noises generated in the power/ground/well/substrate in the high-speed low-power consumption LSIs, and there is a growing demand for measuring and evaluating noises inside the chips in an on-chip manner. Their background arts are disclosed in the Patent Documents 1 to 3.
It is effective for these demands to mount a function to measure the internal signals in LSI chips. Conventionally, it is disclosed that the noise distribution in a chip can be measured by making an array of a detection front-end (FE) circuit configured by including a source follower (SF) circuit and a latch comparator (LC) (refer to the Non-Patent Document 1). However, there has been a problem of high cost since the number of output pins necessary for measurement is great and the required performance of an external measuring instrument is expensive in accordance with the on-chip configuration of only the detection front-end circuit. As a solution measure for the problem, an on-chip configuration of a timing signal generator circuit and a reference voltage generating mechanism in addition to the detection front-end circuit is also proposed (refer to the Non-Patent Document 2). However, a measuring time reduction, a chip area reduction and securing of a measurement accuracy in a multi-channel configuration remain as problems, and it has been insufficient as means for measuring in an on-chip multi-channel manner various waveforms such as noises of internal signals, ground voltages, well voltages, substrate voltages and so on of very large scale integrated circuits.
FIG. 13 is a block diagram showing a configuration of a timing signal generator circuit according to the first prior art. The timing signal generator circuit is configured by connecting in cascade a plurality of delay inverters 101 to 104 and includes a multiplexer 105 to selectively output an output signal of any one of the output signals of inverters 101 to 104. The timing signal generator circuit, which, has such an advantageous effect that a delay step can be discretized by the inverter delay time, has however been unable to avoid an increase in the circuit scale (consumption current) due to an increase in resolution (multi-bit configuration) and has had a problem of large operating noises because all the inverters necessarily operate in selecting whichever delay.
Moreover, in order to solve the problems of the Patent Documents 1 to 3, the present inventor and others propose a sampling timing signal generator circuit for the signal waveform measurement system, the sampling timing signal generator circuit being suitable for an on-chip signal waveform measurement apparatus of which the operating noise is small in comparison with the prior arts in the Patent Documents 4 to 6. The sampling timing signal generator circuit is a sampling timing signal generator circuit that generates a plurality of enable timing signals on the basis of a predetermined system clock signal and a predetermined master clock signal, and the sampling timing signal generator circuit includes a replica DLL (Delayed Locked Loop) circuit that generates a predetermined reference bias voltage in synchronization with the system clock signal on the basis of the system clock signal and outputs the same, and a delay signal generator circuit that generates a current by dividing a reference current corresponding to the reference bias voltage by 1/n (where “n” is an integer not smaller than one) on the basis of the master clock signal and the reference bias voltage, generates a predetermined time delay by multiplying a time interval for charging an output load capacitance by “n” times on the basis of the generated current and generates an enable timing control signal by multiplexing the plurality of enable timing signals by delaying the master clock signal by the delay time. By generating the reference bias voltage by the replica DLL circuit so that the delay time becomes equal to the period of the system clock signal, the delay signal generator circuit is characterized by generating the enable timing signals.
FIG. 14 is a circuit diagram showing a configuration of the sampling timing signal generator circuit according to the second prior art proposed in the Patent Documents 4 to 6. The sampling timing signal generator circuit generates a delay time by generating a current weighted 1/n-fold in a current source 107 controlled by a bias voltage Vbs generated by a bias voltage generator 106, integrating the generated current by a single capacitor 109 via an inverter 108 of a CMOS circuit configured by including MOS field-effect transistors (hereinafter referred to as MOSFETs) Q1 and Q2 and inputting its output voltage as an input voltage Vint to an inverter 110 that operates as a comparator.
Prior Art Documents related to the present invention are as follows:
Patent Document 1: Japanese patent laid-open publication No. JP 10-123215 A;
Patent Document 2: Japanese patent laid-open publication No. JP 2001-077160 A;
Patent Document 3: Japanese patent laid-open publication No. JP 2003-028898 A;
Patent Document 4: Japanese patent No. JP 4150402;
Patent Document 5: U.S. Pat. No. 7,332,916;
Patent Document 6: Japanese patent laid-open publication No. JP 2006-276010 A;
Patent Document 7: Japanese patent laid-open publication No. JP H05-075410 A;
Non-Patent Document 1: Makoto Nagata et al., “Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits”, 2001 Symposium on VLSI Circuits Digest of Technical Papers, #15-1, Kyoto in Japan, pp. 159-162, June 2001;
Non-Patent Document 2: Kouichirou Noguchi et al., “On-chip Power/Ground Measurement Technique”, the 7th system LSI workshop proceedings, hosted by The IEICE Electronics Society Technical Committee on Integrated Circuits and Devices, pp. 287-290, November, 2003; and
Non-Patent Document 3: M. Z. Straayer et al., “An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC”, 2008 IEEE Symposium on VLSI Circuits, pp. 82-83, Jun. 18-20, 2008.
FIG. 15 is a graph showing a delay time characteristic of the bias voltage Vbs of the sampling timing signal generator circuit of FIG. 14 of the second prior art, and FIG. 16 is a graph showing a delay time characteristic of an input voltage Vint to the comparator (configured by including the inverter 110) of the sampling timing signal generator circuit of FIG. 14. In the timing signal generator circuit of the second prior art, in which only a single circuit operates for the generation of the delay time, therefore has such an advantageous effect that the noise is small. However, there have been such problems that a nonlinear bias voltage as shown in FIG. 15 is necessary for the 1/n-fold current value weighting, and a difference of the bias voltage becomes small in a high-resolution (multi-bit) configuration, resulting in deteriorating the linearity and controllability. There has been such a further problem that the input voltage slope of the comparator depends on the code, and nonlinearity occurs in the response of the comparator as shown in FIG. 16.
FIG. 17 is a circuit diagram showing a configuration of a timing generator circuit according to the third prior art disclosed in the Patent Document 7. The timing generator circuit is configured by including an input terminal 201, a buffer amplifier 202, a switch 203, a constant current source 204, a DA converter 209, a mirror amplifier 210 having a mirror capacitance C0, a comparator 207, and an output terminal 208. In the timing generator circuit, the mirror capacitance C0 is discharged by a constant current in a saturation region and a linear region, and a delay time is generated by comparing the inverted input terminal of the mirror amplifier 210 with a constant value VTH. Since the delay time generated in the linear region in which the slope of the ramp waveform is small can be accurately changed by input data, the delay time can be set to a high accuracy and a high resolution. Moreover, by virtue of the comparison with the constant value in the saturation region in which the slope of the ramp waveform is large, a noise resistance can be achieved even when the delay time is long. That is, by changing the equivalent capacity of the mirror amplifier 210, a programmable delay line, of which the configuration is simple, the linearity is good, and high-speed operation is possible, is achieved. However, there has been such a problem that the accuracy of conversion to the delay time is largely degraded since the discharging characteristic becomes nonlinear in the saturation region when the mirror capacitance C0 is discharged by a constant current in the saturation region and the linear region.
The aforementioned various problems of the prior arts are as follows if digested.
In order to actualize an on-chip signal monitor apparatus (refer to, for example, the Non-Patent Documents 4 to 6) for testing the functions of VLSIs or observing the internal states of VLSIs, a high-resolution timing signal generating function on the picosecond order is indispensable. A high-linearity multi-bit digital delay time generating function is required for the reference clock signal.
Regarding the timing generating methods of the prior arts, there is reported a delay chain method by a multistage connection of delay generator circuits in a manner similar to that of the first prior art, a circuit to generate a time interval when an integral voltage reaches a fixed voltage by bias current integration on a single capacitance in a manner similar to that of the second prior art and so on. However, the first prior art, which can generate a delay time with a subpicosecond resolution by, for example, the multistage connection of current control type inverters and an interpolation circuit, however needs an inverter on the 2n order for generating an n-bit delay step, and therefore, the circuit scale is increased. Further, since the multistage connection structure indispensably needs to operate all the stages, increases in the power and noise cannot be avoided. On the other hand, the second prior art, which can generate a multibit delay time with a single current source and a single capacitance, is therefore able to suppress the increase in the circuit scale and the generation of noises. However, since it is necessary for the variability of the delay time to control the integral current amount, and the current amount of the MOS circuit is nonlinear to the control voltage, voltage controllability deteriorates in the multistage configuration, and maintenance of the linearity becomes difficult. In particular, in the third prior art, at the time of discharging the mirror capacitance C0 by a constant current in the saturation region and the linear region, the discharge characteristic becomes nonlinear, in particular, in the saturation region, and therefore, the accuracy of conversion to the delay time is largely degraded.